1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for manufacturing semiconductor devices with reduced critical dimensions.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g, channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires being able to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, preferably in a self-aligned manner. The ability to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, is limited by, among other things, physical limits imposed by photolithography. Diffraction effects impose limits on the critical dimensions of components such as gate conductors and gate dielectrics that correspond roughly to the wavelengths of the light used to perform the photolithography. Retooling wafer fabs to use shorter wavelengths, as in deep ultraviolet (DUV) photolithography and/or in high-energy electron beam lithography, is very expensive.
One conventional approach to achieving reduced critical dimensions, resorting to expensive DUV photolithography and/or high-energy electron beam lithography, is schematically illustrated in FIGS. 1-4. As shown in FIG. 1, for example, a conventional MOS transistor 100 may be formed on a semiconducting substrate 105, such as doped-silicon. The MOS transistor 100 may have a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor such as an N+-doped-poly (P+-doped-poly) gate 110 formed above a gate oxide 115 formed above the semiconducting substrate 105. The N+-doped-poly (P+-doped-poly) gate 110 and the gate oxide 115 may be separated from active areas such as N+-doped (P+-doped) source/drain regions 120 of the MOS transistor 100 by dielectric spacers 125. The dielectric spacers 125 may be formed above Nxe2x88x92-doped (Pxe2x88x92-doped) source/drain extension (SDE) regions 130. As shown in FIG. 1, shallow trench isolation (STI) regions 140 may be provided to isolate the MOS transistor 100 electrically from neighboring semiconductor devices such as other MOS transistors (not shown).
The Nxe2x88x92-doped (Pxe2x88x92-doped) SDE regions 130 are typically provided to reduce the magnitude of the maximum channel electric field found close to the N+-doped (P+-doped) source/drain regions 120 of the MOS transistor 100, and, thereby, to reduce the associated hot-carrier effects. The lower (or lighter) doping of the Nxe2x88x92-doped (Pxe2x88x92-doped) SDE regions 130, relative to the N+-doped (P+-doped) source/drain regions 120 of the MOS transistor 100 (lower or lighter by at least a factor of two or three), reduces the magnitude of the maximum channel electric field found close to the N+-doped (P+-doped) source/drain regions 120 of the MOS transistor 100, but increases the source-to-drain resistances of the Nxe2x88x92-doped (Pxe2x88x92-doped) SDE regions 130.
As shown in FIG. 1, typically the N+-doped-poly (P+-doped-poly) gate 110 and the gate oxide 115 have a critical dimension xcex4DUV that effectively determines a channel length xcex of the MOS transistor 100. The channel length xcex is the distance between the Nxe2x88x92-doped (Pxe2x88x92-doped) SDE regions 130 adjacent the N+-doped-poly (P+-doped-poly) gate 110 and the gate oxide 115.
As shown in FIGS. 2-4, typically the critical dimension xcex4DUV of the N+-doped-poly (P+-doped-poly) gate 110 and the gate oxide 115 is determined as follows. As shown in FIG. 2, a gate oxide layer 215 is formed above the semiconducting substrate 105, and a gate conductor layer 210 is formed above the gate oxide layer 215. An antireflective coating (ARC) layer 230 is formed above the gate conductor layer 210. For the sake of comparison, a photoresist layer 220 is shown, as if formed and patterned using conventional non-DUV photolithography, above the ARC layer 230. The photoresist layer 220 is patterned to have a smallest, non-deep ultraviolet diffraction-limited dimension xcex4non-DUV that may be larger than about 1800 xc3x85.
As shown in FIG. 3, a photoresist mask 320 is formed and patterned, using conventional DUV photolithography and/or high-energy electron beam lithography, above the ARC layer 230. The photoresist layer 220 is indicated in phantom, for the sake of comparison. The photoresist mask 320 will typically have the smallest, deep ultraviolet diffraction-limited critical dimension xcex4DUV that may be about 1800 xc3x85 that will determine the size of the N+-doped-poly (P+-doped-poly) gate 110 and the gate oxide 115.
As shown in FIG. 4, the photoresist mask 320 having the critical dimension xcex4DUV is used as a mask to remove respective portions 410 (shown in phantom) from the gate conductor layer 210 (FIGS. 2-3) to form a gate structure 400 that includes the N+-doped-poly (P+-doped-poly) gate 110 and a portion of the gate oxide layer 215 that will eventually become the gate oxide 115 after subsequent etching and/or processing. The gate structure 400, and, hence the N+-doped-poly (P+-doped-poly) gate 110, will also have the critical dimension xcex4DUV defined by the photoresist mask 320. Nevertheless, the critical dimension xcex4DUV defined by the photoresist mask 320 and total etch is still too large. It would be desirable to have a less expensive technique that would be sufficiently controllable, reliable and feasible to form and pattern components such as gate conductors on even more reduced scales, consistently, robustly and reproducibly, preferably in a self-aligned manner.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.
In another aspect of the present invention, a semiconductor device is provided, formed by a method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.